1. Field of the Invention
The present invention relates to a planarizing coating method that fills a step (gap) between wiring patterns formed on the board surface of a semiconductor wafer, a glass board, and the like on which the wiring pattern is formed.
2. Description of the Related Art
Heretofore, after filling the step between the wiring patterns formed on a semiconductor wafer surface by an insulating coating film (SOG: Spin-on Glass), an interlayer insulating film is formed on the step, and further on the step, a wiring process is performed, thereby forming a three-dimensional circuit. Here, to make the wiring process of the upper layer easy, it is indispensable to evenly form the interlayer insulating film, and various proposals for this purpose have been disclosed.
When the gap of the wiring patterns is filled by the insulating coating film, heretofore, the coating liquid of the same specification has been coated twice. However, according to this method, when an attempt is made to completely fill the gap of the wiring patterns, the coating liquid ends up being thickly adhered also on the pattern crest, and this has created a problem of the lack of flatness of the interlayer insulating film formed on the crest.
Such an example is shown in FIGS. 4A and 4B. On a board W, wiring patterns 100 are formed, and the gap between these patterns is made in the form of a step. The board W having this step is processed by the coating liquid so as to obtain a coating film 101 as shown in FIG. 4A. At this stage, the crest 100a of the wiring pattern 100 is hardly adhered with any coating film, nor is the step flattened.
Hence, to further fill up the step, when a second coating is performed and a coating film 102 is formed as shown in FIG. 4B, the crest 100a ends up being also adhered with a coating film of a considerable thickness. When the coating film adhered on the crest 100a is thick, the flatness of the interlayer insulating film formed on this film is also deteriorated, thereby causing difficulty in the formation of an integrated circuit.
Further, there has been practiced a method also, in which the step between the wiring patterns is filled up with sediment by an HDP (High Density Plasma), and the sediment on the wiring patterns is flattened by abrading by a CMP (Chemical Mechanical Polishing), and after that, the interlayer insulating film is formed by a plasma CVD (Chemical Vapor Deposition).
Further, Japanese Patent Laid-Open No. 2003-230860 (Patent Document 1) discloses a coating device to coat a plurality of liquids with viscosities different from one another on the board. Specifically, the coating by the liquids with viscosities different from one another is performed corresponding to the arrangement of the step between the wiring patterns, so that the steps of the board can be effectively removed.
According to the method, in which the step between the wiring patterns is filled up with the sediment by the HDP, and the sediment on the wiring patterns is abraded by the CMP so as to be flattened, and after that, the interlayer insulating film is formed by the plasma CVD, sufficient flatness can be obtained. However, the employment of the HDP and the CMP requires expensive equipment and the cost thereof is high, and this is not a simple method. In addition, there is a problem of the wasting and the like of raw materials due to a large consumption of energy by the employment of the HDP and the CMP and the abrading of the sediment.
Further, the coating device as disclosed in Japanese Patent Laid-Open No. 2003-230860 (Patent Document 1) is unable to effectively prevent a problem of the coating liquid thickly adhering on the pattern crest.